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ISL43L210
Data Sheet March 15, 2005 FN6131.0
Ultra Low ON-Resistance, +1.1V to +4.5V Single Supply, SPDT Analog Switch
The Intersil ISL43L210 device is a low ON-resistance, low voltage, bidirectional, single pole/double throw (SPDT) analog switch designed to operate from a single +1.1V to +4.5V supply. Targeted applications include battery powered equipment that benefit from low on-resistance and fast switching speeds (tON = 7ns, tOFF = 3ns). The digital logic input is 1.8V CMOS compatible when using a single +3V supply. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL43L210 is offered in a 6 lead SC70 package, alleviating board space limitations. The ISL43L210 is a committed SPDT that consist of one normally open (NO) and one normally closed (NC) switch. This configuration can also be used as a 2-to-1 multiplexer.
TABLE 1. FEATURES AT A GLANCE Number of Switches SW 1.8V RON 1.8V tON/tOFF 3V RON 3V tON/tOFF 4.3V RON 4.3V tON/tOFF Package 1 SPDT or 2-1 MUX 0.75 16ns/5ns 0.38 8ns/4ns 0.34 7ns/3ns 6 Ld SC70
Features
* Pb-free available (RoHS compliant) * Drop In replacement for the MAX4714 * ON resistance (RON) - VCC = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.34 - VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.38 - VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 * RON matching between channels . . . . . . . . . . . . . . . 0.002 * RON flatness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.06 * Single supply operation . . . . . . . . . . . . . . . . . +1.1V to +4.5V * Fast switching action (+3.9V Supply) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3ns * Guaranteed break-before-make * ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV * 1.8V CMOS logic compatible (+3V supply) * 6 lead SC70 package
Applications
* Battery powered, handheld, and portable equipment - Cellular/mobile phones - Pagers - Laptops, notebooks, palmtops * Portable test and measurement * Medical equipment * Audio and video switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL43L210 Pinout
(Note 1) ISL43L210 (SC70) TOP VIEW
Ordering Information
PART NO. (BRAND)
6 NO 5 COM 4 NC
TEMP. RANGE (C) -40 to 85 -40 to 85
PACKAGE 6 Ld SC70 Tape and Reel
PKG. DWG. # P6.049
IN 1 V+ 2 GND 3
ISL43L210IH-T (CMA) ISL43L210IHZ-T (CMA) (See Note)
6 Ld SC70 P6.049 Tape and Reel (Pb-free)
NOTE: 1. Switches Shown for Logic "0" Input.
Truth Table
LOGIC 0 1 NOTE: PIN NC On Off PIN NO Off On
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
Pin Descriptions
PIN V+ GND IN COM NO NC FUNCTION System Power Supply Input (+1.1V to +4.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
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Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 150mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 300mA ESD Rating: HBM > . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1000V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 6 Ld SC70 Package . . . . . . . . . . . . . . . . . . . . . . . . . 590 Maximum Junction Temperature (Plastic Package). . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 3.9V, ICOM = 100mA, VNO or VNC = 2.2V (See Figure 5) V+ = 3.9V, ICOM = 100mA, VNO or VNC = 2.2V 25 Full 25 Full V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0.8V, 2.2V, 3.5V, (Note 7) V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating 25 Full
0 -30 -100 -30 -100
0.36 0.4 0.002 0.003 0.06 0.08 -
V+ 30 100 30 -100
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 3.9V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 4.5V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3, Note 8) VG = V+/2, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6)
25 Full 25 Full Full 25 25 25
1 -
7 3 3 25 -70 -70
15 20 10 15 -
ns ns ns ns ns pC dB dB
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
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Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified (Continued) TEST CONDITIONS f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 TEMP (C) 25 25 25 (NOTE 5) MIN TYP 0.006 40 100 (NOTE 5) MAX UNITS % pF pF
PARAMETER Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ =+4.5V, VIN = 0V or V+ Full 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Guaranteed but not tested. V+ = 4.5V, VIN = 0V or V+ (Note 8) Full Full Full 1.6 -0.5 0.5 0.5 V V A 1.1 4.5 0.05 0.4 V A A
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 1.5V (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 1.5V 25 Full 25 Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0.6V, 1.5V, 2.1V (Note 7) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating 25 Full
0 -
0.44 0.005 0.06 0.9 8 0.9 17
V+ 0.6 0.7 0.03 0.05 0.1 0.12 -
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 3.0V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3, Note 8)
25 Full 25 Full Full
1
8 4 4
15 20 10 15 -
ns ns ns ns ns
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
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ISL43L210
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified (Continued) TEST CONDITIONS VG = V+/2, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 TEMP (C) 25 25 25 25 25 25 (NOTE 5) MIN TYP 22 -70 -70 0.006 40 100 (NOTE 5) MAX UNITS pC dB dB % pF pF
PARAMETER Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ (Note 8) Full Full Full 1.4 -0.5 0.5 0.5 V V A 0.018 0.13 A A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0.9V (See Figure 5) V+ = 1.8V, VCOM = 0.3V, 1.5V, VNO or VNC = 1.5V, 0.3V 25 Full 25 Full V+ = 1.8V, VCOM = 0.3V, 1.5V, or VNO or VNC = 0.3V, 1.5V, or Floating 25 Full
0 -
0.75 0.3 7 0.9 18
V+ 0.9 1 -
V nA nA nA nA
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1, Note 8) V+ = 1.8V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3, Note 8) VG = V+/2, RG = 0, CL = 1.0nF (See Figure 2)
25 Full 25 Full Full 25
2 -
16 5 5 15
22 25 12 15 -
ns ns ns ns ns pC
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 1.8V, VIN = 0V or V+ 25 Full 0.018 0.13 A A
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Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 6), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL
Full Full V+ = 1.1V, VIN = 0V or V+ (Note 8) Full
1 -0.5
-
0.4 0.5
V V A
Electrical Specifications - 1.1V Supply
Test Conditions: V+ = +1.1V, GND = 0V, VINH = 1.0V, VINL = 0.3V (Note 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 1.1V, ICOM = 100mA, VNO or VNC = 0.6 (See Figure 5) 25 Full
0 -
2.8 3.5
V+ -
V
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.1V, VNO or VNC = 1.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.1V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1) V+ = 1.1V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 3) 25 Full 25 Full Full 25 28 7 10 9 ns ns ns ns ns
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Full Full 0.4 0.58 V V
Test Circuits and Waveforms
V+ V+ LOGIC INPUT 50% 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON VOUT 90% tr < 5ns tf < 5ns SWITCH INPUT NO or NC COM IN LOGIC INPUT GND RL 50 CL 35pF VOUT C
Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R
L ( ON )
FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES
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ISL43L210 Test Circuits and Waveforms (Continued)
V+ C
SWITCH OUTPUT VOUT ON
VOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V
VG
GND
IN
CL LOGIC INPUT
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
V+ LOGIC INPUT 0V
VNX
NO COM NC IN RL 50 GND
VOUT CL 35pF
SWITCH OUTPUT VOUT
90% 0V
LOGIC INPUT
tD
CL includes fixture and stray capacitance. FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME
FIGURE 3A. MEASUREMENT POINTS
V+ C SIGNAL GENERATOR RON = V1/100mA
NO or NC NO or NC
V+ C
VNX IN 0V or V+
100mA V1 IN 0V or V+
ANALYZER RL
COM
COM
GND
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
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ISL43L210 Test Circuits and Waveforms (Continued)
V+ C V+ C 50 NO or NC COM
NO or NC
IN1 0V or V+
SIGNAL GENERATOR
IN IMPEDANCE ANALYZER
COM
0V or V+
ANALYZER RL
NC or NO GND
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL43L210 is a bidirectional, single pole/double throw (SPDT) analog switch that offers precise switching capability from a single +1.1V to +4.5V supply with low on-resistance (0.34) and high speed operation (tON = 7ns, tOFF = 3ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.1V), low power consumption (1.8W max), low leakage currents (100nA max), and the tiny SC70 packaging. The ultra low onresistance and Ron flatness provide very low insertion loss and distortion to application that require signal reproduction.
purpose of using a low RON switch. Connecting schottky diodes to the signal pins as shown in Figure 8 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current.
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR
INX VNX VCOM
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the
OPTIONAL SCHOTTKY DIODE
GND
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43L210 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L210 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 4.2V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.1V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details.
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ISL43L210
V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 3.6V (See Figure 17). At 3.6V the VIH level is about 1.1V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 90MHz (See Figure 18). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 19 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 70dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
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ISL43L210 Typical Performance Curves TA = 25C, Unless Otherwise Specified
0.5 ICOM = 100mA 2.5 0.45 V+ = 2.7V RON () RON (W) 2 V+ = 1.1V 1.5 V+ = 1.5V 3 ICOM = 100mA
0.4
V+ = 3V
0.35
V+ = 3.6V V+ = 4.3V
1
0.5
V+ = 1.62V
V+ = 1.8V
0.3
0 0 1 2 VCOM (V) 3 4 5
0
0.5
1 VCOM (V)
1.5
2
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.55 V+ = 4.3V ICOM = 100mA
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.65 0.6 0.55 0.5 0.45 25C 0.4 0.35 -40C V+ = 2.7V ICOM = 100mA
0.5
0.45 RON () RON ()
0.4
85C
85C
0.35 25C 0.3 -40C 0.25 0 1 2 VCOM (V) 3 4 5
0.3 0 0.5 1 1.5 VCOM (V) 2 2.5 3
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
0.8 85C 0.7
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
100
V+ = 1.8V ICOM = 10mA
50 0.6 RON () 25C Q (pC) 0 V+ = 1.8V V+ = 3V
-40C 0.5
0.4
-50
V+ = 4.2V 0.3 0 0.5 1 VCOM (V) 1.5 2 -100 0 1 2 VCOM (V) 3 4 5
FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. CHARGE INJECTION vs SWITCH VOLTAGE
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ISL43L210 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
30 7
25
6
tON (ns)
tOFF (ns)
20
5 85C 4 -40C
15 85C 25C 10 -40C 5 1 1.5 2 2.5 V+ (V) 3 3.5 4 4.5
3
25C
2
1
1.5
2
2.5 V+ (V)
3
3.5
4
4.5
FIGURE 15. TURN-ON TIME vs SUPPLY VOLTAGE
1.3 NORMALIZED GAIN (dB) 1.2 1.1 1 VINH AND VINL (V) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1 1.5 2 2.5 V+ (V) 3 3.5 4 4.5 VINL VINH
FIGURE 16. TURN-OFF TIME vs SUPPLY VOLTAGE
V+ = 1.1V to 4.5V GAIN 0 -20 PHASE 0 20 40 60 RL = 50 VIN = 0.2VP-P to 2.8VP-P (V+ = 3.0V) 1 10 FREQUENCY (MHz) 100 80 300 PHASE (DEGREES)
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
0 V+ = 1.1V to 4.5V -10 -20 -30 CROSSTALK (dB) -40 -50 -60 CROSSTALK -70 -80 -90 -100 1K 10K 100K 1M 10M 70 80 90 100 100M 500M ISOLATION 10 20 OFF ISOLATION (dB) 30 40 50 60 0
FIGURE 18. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 57 PROCESS: Submicron CMOS
FREQUENCY (Hz)
FIGURE 19. CROSSTALK AND OFF ISOLATION
11
FN6131.0 March 15, 2005
ISL43L210 Small Outline Transistor Plastic Packages (SC70-6)
0.20 (0.008) M C L b e C VIEW C
P6.049
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES SYMBOL A MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045 MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053 MILLIMETERS MIN 0.80 0.00 0.00 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 NOTES -
6 C L 1
5
4 C L E E1
A1 A2 b b1 c c1 D E E1 e e1 L L1 L2 N R R1
2
3
e1 D C L
C
A
A2
A1
SEATING PLANE -C-
0.0256 Ref 0.0512 Ref 0.010 0.018 0.017 Ref. 0.006 BSC 6 0.004 0.004 0o 0.010 8o
0.65 Ref 1.30 Ref 0.26 0.46 0.420 Ref. 0.15 BSC 6 0.10 0.15 0o 0.25 8o
0.10 (0.004) C
WITH PLATING c
b b1 c1
5
NOTES:
Rev. 2 9/03
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C L1
2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
L2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6131.0 March 15, 2005

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